1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device including high voltage withstand transistors with an improved element isolation area for use as a high voltage withstand section of a large LC (liquid crystal) driver type LSI.
2. Description of the Related Art
A guard ring system has so far been employed as a technique for forming an element isolation area in a high voltage withstand transistor.
In a high voltage withstand transistor, for example, a polysilicon connection layer which is the electrode of that transistor is formed in contact with drain and source regions formed in the upper surface portion of a semiconductor substrate. A field oxide film is formed around the drain and source regions and a guard ring is formed around the field oxide film and has a predetermined impurity concentration.
In the arrangement of the high voltage withstand transistor, the polysilicon connection layer providing the electrodes of the transistor is situated over the guard ring in an intersecting way. For the guard ring of a p-type (n-type), for example, the guard ring portion which is situated just over that polysilicon connection layer is inverted to an n-type (p-type) at about 10 V.
Therefore, a device whose withstand voltage exceeding 30 V is usually of such a type as shown in FIG. 1A and 1B. FIG. 1A is a plan view showing an array pattern of a high voltage withstand transistor of the prior art and FIG. 1B is a cross-sectional view showing the transistor of FIG. 1A.
In FIGS. 1A and 1B, a drain/source area 14 is formed in the upper surface portion of a semiconductor substrate 12 and a field oxide film 16a of about 10000.ANG. in thickness is formed around the drain/source area 14 at a predetermined interval. A guide ring 18 is formed around the field oxide film 16a such that it is situated near the field oxide film 16b. On that portion of the upper surface of the substrate 12, including the surface portion of the drain/source area 14, which is surrounded with the field oxide film 16a, a gate oxide film 20 is formed as an insulating film. A polysilicon connection layer 22 is formed on the gate oxide film 20 and field oxide film 16a. A field oxide film 24 is formed on the polysilicon connection layer 22, field oxide film 16b and guard ring 18. Aluminum interconnection layers 28a and 28b are connected respectively via contact areas 26a and 26b to the polysilicon connection layer 22 just over the field oxide film 16a. In order to make an inversion threshold voltage of the guard ring 18 high, the aluminum interconnection layers 28a and 28b are patterned after the field oxide films 16a, 16b and 24 have been formed.
In the conventional high voltage withstand transistor thus arranged, it is possible to raise the withstand voltage if the guard ring 18 is employed as element isolation for the high voltage withstand transistor.
However, the aluminum interconnection layers 28a and 28b are used at an intersecting location of the guard ring 18, requiring contact areas 26a and 26b between the polysilicon connection layer 22 and the aluminum interconnection layers 28a and 28b. Thus the field oxide layer is necessary for the formation of the contact areas 26a and 26b, unavoidably leading to an increase in the chip size of the transistor and hence to a cost problem.